A Systolic String Matching Algorithm for High-Speed Recognition of a Restricted Regular Set

This paper proposes a systolic string matching algorithm for high-speed recognition of a restricted regular set, in which a pattern is specified by a class of restricted regular expressions. The architecture of the proposed systolic algorithm is a one-dimensional array of simple processing units. The algorithm can accept a pattern including Kleene-closure operations, such as ab(cde|fg)∗(hi|j)k, which could not be accepted with existing one-dimensional systolic string matching algorithms. Experiments show that the proposed algorithm implemented on an FPGA chip achieves a high throughput of 1.456 Gigabits per second.